A number of chemical-mechanical polishing (CMP) operations are used in both front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) processing of semiconductor devices. For example, the following CMP operations are commonly employed. Shallow trench isolation (STI) is an FEOL process used prior to formation of the transistors. A dielectric such as tetraethyl orthosilicate (TEOS) is deposited in openings formed in the silicon wafer. A CMP process is then used to remove the excess TEOS resulting in a structure in which a predetermined pattern of TEOS is inlaid in the silicon wafer. Tungsten plug and interconnect and copper interconnect and dual damascene processes are BEOL processes used to form the network of metal wires that connect the device transistors. In these processes tungsten or copper metal is deposited in openings formed in a dielectric material (e.g., TEOS). CMP processes are used to remove the excess tungsten or copper from the dielectric to form tungsten or copper plugs and/or interconnects therein. An interlayer dielectric (ILD) material (such as TEOS) is deposited between metal interconnect levels to provide electrical insulation between the levels. An ILD CMP step is commonly employed to smooth and planarize the deposited insulating material prior to building up the subsequent interconnect level.
In a conventional CMP operation, the substrate (wafer) to be polished is mounted on a carrier (polishing head) which is in turn mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus (polishing tool). The carrier assembly provides a controllable pressure to the substrate, pressing the substrate against the polishing pad. A chemical-mechanical polishing composition is generally applied to the surface of the pad while the substrate and pad are moved relative to one another. The relative motion of the substrate and pad (and the applied polishing composition) abrades and removes a portion of the material from the surface of the substrate, thereby polishing the substrate. Polishing of the substrate is generally aided by the chemical activity of the polishing composition (e.g., by a chemical accelerator) and/or the mechanical activity of an abrasive suspended in the polishing composition.
Chemical-mechanical polishing compositions and methods for polishing (or planarizing) the surface of a substrate are well known in the art. Polishing compositions (also known as slurries) for polishing dielectrics commonly include silica or ceria abrasives. Those utilizing silica abrasives commonly have a high pH and a high silica concentration (e.g., greater than 12 weight percent). Polishing compositions for polishing metal layers (such as tungsten or copper) commonly include silica or alumina abrasives as well as various chemical accelerators, such as oxidizers, chelating agents, catalysts, and the like.
As is well known in the art, the semiconductor industry is subject to continuing and severe downward pricing pressure. In order to maintain economically favorable CMP processes, high throughput is required thereby necessitating high removal rates of the primary material being polished (e.g., an ILD CMP process may require a high removal rate of TEOS while a tungsten CMP process may require a high removal rate of tungsten). The downward pricing pressure also extends to the CMP consumables themselves (e.g., to the CMP slurries and pads). Such pricing pressure poses a challenge to the slurry formulator as the pressure to reduce costs often conflicts with the desired slurry performance metrics. There is a real need in the industry for CMP slurries that provide high throughput at reduced overall costs.